This invention relates to superconducting digital electronic circuits and, more particularly, to superconducting gate array cells.
Superconducting digital logic gates which utilize Josephson junctions have been under investigation for a number of years. One family of superconducting logic gates known as modified variable threshold logic (MVTL) gates, has been successfully used to construct various types of superconducting digital devices. Examples of such devices can be found in Fujimaki et al., "Josephson 8-Bit Shift Register", IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, October 1987, and Fujimaki et al., "Josephson Pseudorandom Bit-Sequence Generator", IEEE Journal of Solid State Circuits, Vol. 23, No. 3, June 1988. These references utilize an MVTL OR gate which has the advantage of a wide operating margin while occupying a relatively small cross-sectional area. In this gate, if a logic 1 is applied to either or both input lines, then a logic 1 is produced at an output line, otherwise a logic 0 is produced. This condition holds for positive logic in which TRUE=1 and FALSE=0. For negative logic in which TRUE=1 and FALSE=0, an AND gate is produced. In each case, the input, output and bias signals are in phase signals. If the bias for the circuit is supplied from a leading phase power supply relative to the input signal, then the circuit not only performs the desired logic function, but the output signal is shifted relative to the input signal.
Since an inphase inverter gate cannot be fabricated using Josephson junction technology, MVTL OR and AND gates have been used in dual-rail circuits. By combining two MVTL OR gates with an unbuffered AND gate, a standard cell for rapidly prototyping superconducting dual-rail logic circuits has been produced as shown in the above-cited references. This cell has been used to build numerous digital circuits, all implemented in dual-rail logic.
Although an inphase inverter cannot be made using Josephson junction technology, a timed inverter has been constructed as shown in the above references. With the timed inverter, an input signal is provided inphase with a first phase of a power supply and an output signal is produced which is inphase with a second phase of the power supply. This inverter has been used to implement dual-rail logic by generating an inverted signal and synchronizing the main signal with the inverted signal using an MVTL OR gate powered by the second phase of the power supply.
Dual-rail logic circuits can have twice the amount of circuitry required in single-rail equivalents. However, to implement single-rail logic, signal inversion must be accomplished. It would be desirable to achieve. NOR and NAND functions in single-rail circuits which can be used to construct various logic circuits.